467 lines
22 KiB
Python
467 lines
22 KiB
Python
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"""
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pygments.lexers.hdl
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~~~~~~~~~~~~~~~~~~~
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Lexers for hardware descriptor languages.
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:copyright: Copyright 2006-2024 by the Pygments team, see AUTHORS.
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:license: BSD, see LICENSE for details.
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"""
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import re
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from pygments.lexer import RegexLexer, bygroups, include, using, this, words
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from pygments.token import Text, Comment, Operator, Keyword, Name, String, \
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Number, Punctuation, Whitespace
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__all__ = ['VerilogLexer', 'SystemVerilogLexer', 'VhdlLexer']
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class VerilogLexer(RegexLexer):
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"""
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For verilog source code with preprocessor directives.
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"""
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name = 'verilog'
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aliases = ['verilog', 'v']
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filenames = ['*.v']
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mimetypes = ['text/x-verilog']
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url = 'https://en.wikipedia.org/wiki/Verilog'
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version_added = '1.4'
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#: optional Comment or Whitespace
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_ws = r'(?:\s|//.*?\n|/[*].*?[*]/)+'
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tokens = {
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'root': [
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(r'^\s*`define', Comment.Preproc, 'macro'),
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(r'\s+', Whitespace),
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(r'(\\)(\n)', bygroups(String.Escape, Whitespace)), # line continuation
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(r'/(\\\n)?/(\n|(.|\n)*?[^\\]\n)', Comment.Single),
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(r'/(\\\n)?[*](.|\n)*?[*](\\\n)?/', Comment.Multiline),
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(r'[{}#@]', Punctuation),
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(r'L?"', String, 'string'),
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(r"L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'", String.Char),
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(r'(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?', Number.Float),
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(r'(\d+\.\d*|\.\d+|\d+[fF])[fF]?', Number.Float),
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(r'([0-9]+)|(\'h)[0-9a-fA-F]+', Number.Hex),
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(r'([0-9]+)|(\'b)[01]+', Number.Bin),
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(r'([0-9]+)|(\'d)[0-9]+', Number.Integer),
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(r'([0-9]+)|(\'o)[0-7]+', Number.Oct),
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(r'\'[01xz]', Number),
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(r'\d+[Ll]?', Number.Integer),
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(r'[~!%^&*+=|?:<>/-]', Operator),
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(r'[()\[\],.;\']', Punctuation),
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(r'`[a-zA-Z_]\w*', Name.Constant),
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(r'^(\s*)(package)(\s+)', bygroups(Whitespace, Keyword.Namespace, Text)),
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(r'^(\s*)(import)(\s+)', bygroups(Whitespace, Keyword.Namespace, Text),
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'import'),
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(words((
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'always', 'always_comb', 'always_ff', 'always_latch', 'and',
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'assign', 'automatic', 'begin', 'break', 'buf', 'bufif0', 'bufif1',
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'case', 'casex', 'casez', 'cmos', 'const', 'continue', 'deassign',
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'default', 'defparam', 'disable', 'do', 'edge', 'else', 'end', 'endcase',
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'endfunction', 'endgenerate', 'endmodule', 'endpackage', 'endprimitive',
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'endspecify', 'endtable', 'endtask', 'enum', 'event', 'final', 'for',
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'force', 'forever', 'fork', 'function', 'generate', 'genvar', 'highz0',
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'highz1', 'if', 'initial', 'inout', 'input', 'integer', 'join', 'large',
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'localparam', 'macromodule', 'medium', 'module', 'nand', 'negedge',
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'nmos', 'nor', 'not', 'notif0', 'notif1', 'or', 'output', 'packed',
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'parameter', 'pmos', 'posedge', 'primitive', 'pull0', 'pull1',
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'pulldown', 'pullup', 'rcmos', 'ref', 'release', 'repeat', 'return',
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'rnmos', 'rpmos', 'rtran', 'rtranif0', 'rtranif1', 'scalared', 'signed',
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'small', 'specify', 'specparam', 'strength', 'string', 'strong0',
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'strong1', 'struct', 'table', 'task', 'tran', 'tranif0', 'tranif1',
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'type', 'typedef', 'unsigned', 'var', 'vectored', 'void', 'wait',
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'weak0', 'weak1', 'while', 'xnor', 'xor'), suffix=r'\b'),
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Keyword),
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(words((
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'accelerate', 'autoexpand_vectornets', 'celldefine', 'default_nettype',
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'else', 'elsif', 'endcelldefine', 'endif', 'endprotect', 'endprotected',
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'expand_vectornets', 'ifdef', 'ifndef', 'include', 'noaccelerate',
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'noexpand_vectornets', 'noremove_gatenames', 'noremove_netnames',
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'nounconnected_drive', 'protect', 'protected', 'remove_gatenames',
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'remove_netnames', 'resetall', 'timescale', 'unconnected_drive',
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'undef'), prefix=r'`', suffix=r'\b'),
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Comment.Preproc),
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(words((
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'bits', 'bitstoreal', 'bitstoshortreal', 'countdrivers', 'display', 'fclose',
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'fdisplay', 'finish', 'floor', 'fmonitor', 'fopen', 'fstrobe', 'fwrite',
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'getpattern', 'history', 'incsave', 'input', 'itor', 'key', 'list', 'log',
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'monitor', 'monitoroff', 'monitoron', 'nokey', 'nolog', 'printtimescale',
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'random', 'readmemb', 'readmemh', 'realtime', 'realtobits', 'reset',
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'reset_count', 'reset_value', 'restart', 'rtoi', 'save', 'scale', 'scope',
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'shortrealtobits', 'showscopes', 'showvariables', 'showvars', 'sreadmemb',
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'sreadmemh', 'stime', 'stop', 'strobe', 'time', 'timeformat', 'write'),
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prefix=r'\$', suffix=r'\b'),
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Name.Builtin),
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(words((
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'byte', 'shortint', 'int', 'longint', 'integer', 'time',
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'bit', 'logic', 'reg', 'supply0', 'supply1', 'tri', 'triand',
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'trior', 'tri0', 'tri1', 'trireg', 'uwire', 'wire', 'wand', 'wor'
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'shortreal', 'real', 'realtime'), suffix=r'\b'),
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Keyword.Type),
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(r'[a-zA-Z_]\w*:(?!:)', Name.Label),
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(r'\$?[a-zA-Z_]\w*', Name),
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(r'\\(\S+)', Name),
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],
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'string': [
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(r'"', String, '#pop'),
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(r'\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})', String.Escape),
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(r'[^\\"\n]+', String), # all other characters
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(r'(\\)(\n)', bygroups(String.Escape, Whitespace)), # line continuation
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(r'\\', String), # stray backslash
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],
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'macro': [
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(r'[^/\n]+', Comment.Preproc),
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(r'/[*](.|\n)*?[*]/', Comment.Multiline),
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(r'//.*?\n', Comment.Single, '#pop'),
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(r'/', Comment.Preproc),
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(r'(?<=\\)\n', Comment.Preproc),
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(r'\n', Whitespace, '#pop'),
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],
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'import': [
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(r'[\w:]+\*?', Name.Namespace, '#pop')
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]
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}
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def analyse_text(text):
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"""Verilog code will use one of reg/wire/assign for sure, and that
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is not common elsewhere."""
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result = 0
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if 'reg' in text:
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result += 0.1
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if 'wire' in text:
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result += 0.1
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if 'assign' in text:
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result += 0.1
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return result
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class SystemVerilogLexer(RegexLexer):
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"""
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Extends verilog lexer to recognise all SystemVerilog keywords from IEEE
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1800-2009 standard.
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"""
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name = 'systemverilog'
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aliases = ['systemverilog', 'sv']
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filenames = ['*.sv', '*.svh']
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mimetypes = ['text/x-systemverilog']
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url = 'https://en.wikipedia.org/wiki/SystemVerilog'
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version_added = '1.5'
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#: optional Comment or Whitespace
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_ws = r'(?:\s|//.*?\n|/[*].*?[*]/)+'
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tokens = {
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'root': [
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(r'^(\s*)(`define)', bygroups(Whitespace, Comment.Preproc), 'macro'),
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(r'^(\s*)(package)(\s+)', bygroups(Whitespace, Keyword.Namespace, Whitespace)),
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(r'^(\s*)(import)(\s+)', bygroups(Whitespace, Keyword.Namespace, Whitespace), 'import'),
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(r'\s+', Whitespace),
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(r'(\\)(\n)', bygroups(String.Escape, Whitespace)), # line continuation
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(r'/(\\\n)?/(\n|(.|\n)*?[^\\]\n)', Comment.Single),
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(r'/(\\\n)?[*](.|\n)*?[*](\\\n)?/', Comment.Multiline),
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(r'[{}#@]', Punctuation),
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(r'L?"', String, 'string'),
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(r"L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'", String.Char),
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(r'(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?', Number.Float),
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(r'(\d+\.\d*|\.\d+|\d+[fF])[fF]?', Number.Float),
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(r'([1-9][_0-9]*)?\s*\'[sS]?[bB]\s*[xXzZ?01][_xXzZ?01]*',
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Number.Bin),
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(r'([1-9][_0-9]*)?\s*\'[sS]?[oO]\s*[xXzZ?0-7][_xXzZ?0-7]*',
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Number.Oct),
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(r'([1-9][_0-9]*)?\s*\'[sS]?[dD]\s*[xXzZ?0-9][_xXzZ?0-9]*',
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Number.Integer),
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(r'([1-9][_0-9]*)?\s*\'[sS]?[hH]\s*[xXzZ?0-9a-fA-F][_xXzZ?0-9a-fA-F]*',
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Number.Hex),
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(r'\'[01xXzZ]', Number),
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(r'[0-9][_0-9]*', Number.Integer),
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(r'[~!%^&*+=|?:<>/-]', Operator),
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(words(('inside', 'dist'), suffix=r'\b'), Operator.Word),
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(r'[()\[\],.;\'$]', Punctuation),
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(r'`[a-zA-Z_]\w*', Name.Constant),
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(words((
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'accept_on', 'alias', 'always', 'always_comb', 'always_ff',
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'always_latch', 'and', 'assert', 'assign', 'assume', 'automatic',
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'before', 'begin', 'bind', 'bins', 'binsof', 'break', 'buf',
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'bufif0', 'bufif1', 'case', 'casex', 'casez', 'cell',
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'checker', 'clocking', 'cmos', 'config',
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'constraint', 'context', 'continue', 'cover', 'covergroup',
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'coverpoint', 'cross', 'deassign', 'default', 'defparam', 'design',
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'disable', 'do', 'edge', 'else', 'end', 'endcase',
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'endchecker', 'endclocking', 'endconfig', 'endfunction',
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'endgenerate', 'endgroup', 'endinterface', 'endmodule', 'endpackage',
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'endprimitive', 'endprogram', 'endproperty', 'endsequence',
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'endspecify', 'endtable', 'endtask', 'enum', 'eventually',
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'expect', 'export', 'extern', 'final', 'first_match',
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'for', 'force', 'foreach', 'forever', 'fork', 'forkjoin', 'function',
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'generate', 'genvar', 'global', 'highz0', 'highz1', 'if', 'iff',
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'ifnone', 'ignore_bins', 'illegal_bins', 'implies', 'implements', 'import',
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'incdir', 'include', 'initial', 'inout', 'input',
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'instance', 'interconnect', 'interface', 'intersect', 'join',
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'join_any', 'join_none', 'large', 'let', 'liblist', 'library',
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'local', 'localparam', 'macromodule', 'matches',
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'medium', 'modport', 'module', 'nand', 'negedge', 'nettype', 'new', 'nexttime',
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'nmos', 'nor', 'noshowcancelled', 'not', 'notif0', 'notif1', 'null',
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'or', 'output', 'package', 'packed', 'parameter', 'pmos', 'posedge',
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'primitive', 'priority', 'program', 'property', 'protected', 'pull0',
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'pull1', 'pulldown', 'pullup', 'pulsestyle_ondetect',
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'pulsestyle_onevent', 'pure', 'rand', 'randc', 'randcase',
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'randsequence', 'rcmos', 'ref',
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'reject_on', 'release', 'repeat', 'restrict', 'return', 'rnmos',
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'rpmos', 'rtran', 'rtranif0', 'rtranif1', 's_always', 's_eventually',
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's_nexttime', 's_until', 's_until_with', 'scalared', 'sequence',
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'showcancelled', 'small', 'soft', 'solve',
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'specify', 'specparam', 'static', 'strong', 'strong0',
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'strong1', 'struct', 'super', 'sync_accept_on',
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'sync_reject_on', 'table', 'tagged', 'task', 'this', 'throughout',
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'timeprecision', 'timeunit', 'tran', 'tranif0', 'tranif1',
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'typedef', 'union', 'unique', 'unique0', 'until',
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'until_with', 'untyped', 'use', 'vectored',
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'virtual', 'wait', 'wait_order', 'weak', 'weak0',
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'weak1', 'while', 'wildcard', 'with', 'within',
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'xnor', 'xor'),
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suffix=r'\b'),
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Keyword),
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(r'(class)(\s+)([a-zA-Z_]\w*)',
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bygroups(Keyword.Declaration, Whitespace, Name.Class)),
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(r'(extends)(\s+)([a-zA-Z_]\w*)',
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bygroups(Keyword.Declaration, Whitespace, Name.Class)),
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(r'(endclass\b)(?:(\s*)(:)(\s*)([a-zA-Z_]\w*))?',
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bygroups(Keyword.Declaration, Whitespace, Punctuation, Whitespace, Name.Class)),
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(words((
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# Variable types
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'bit', 'byte', 'chandle', 'const', 'event', 'int', 'integer',
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'logic', 'longint', 'real', 'realtime', 'reg', 'shortint',
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'shortreal', 'signed', 'string', 'time', 'type', 'unsigned',
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'var', 'void',
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# Net types
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'supply0', 'supply1', 'tri', 'triand', 'trior', 'trireg',
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'tri0', 'tri1', 'uwire', 'wand', 'wire', 'wor'),
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suffix=r'\b'),
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Keyword.Type),
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(words((
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'`__FILE__', '`__LINE__', '`begin_keywords', '`celldefine',
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'`default_nettype', '`define', '`else', '`elsif', '`end_keywords',
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'`endcelldefine', '`endif', '`ifdef', '`ifndef', '`include',
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'`line', '`nounconnected_drive', '`pragma', '`resetall',
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'`timescale', '`unconnected_drive', '`undef', '`undefineall'),
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suffix=r'\b'),
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Comment.Preproc),
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(words((
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# Simulation control tasks (20.2)
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'$exit', '$finish', '$stop',
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# Simulation time functions (20.3)
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'$realtime', '$stime', '$time',
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# Timescale tasks (20.4)
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'$printtimescale', '$timeformat',
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# Conversion functions
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'$bitstoreal', '$bitstoshortreal', '$cast', '$itor',
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'$realtobits', '$rtoi', '$shortrealtobits', '$signed',
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'$unsigned',
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# Data query functions (20.6)
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'$bits', '$isunbounded', '$typename',
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# Array query functions (20.7)
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'$dimensions', '$high', '$increment', '$left', '$low', '$right',
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'$size', '$unpacked_dimensions',
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# Math functions (20.8)
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'$acos', '$acosh', '$asin', '$asinh', '$atan', '$atan2',
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'$atanh', '$ceil', '$clog2', '$cos', '$cosh', '$exp', '$floor',
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||
|
|
'$hypot', '$ln', '$log10', '$pow', '$sin', '$sinh', '$sqrt',
|
||
|
|
'$tan', '$tanh',
|
||
|
|
# Bit vector system functions (20.9)
|
||
|
|
'$countbits', '$countones', '$isunknown', '$onehot', '$onehot0',
|
||
|
|
# Severity tasks (20.10)
|
||
|
|
'$info', '$error', '$fatal', '$warning',
|
||
|
|
# Assertion control tasks (20.12)
|
||
|
|
'$assertcontrol', '$assertfailoff', '$assertfailon',
|
||
|
|
'$assertkill', '$assertnonvacuouson', '$assertoff', '$asserton',
|
||
|
|
'$assertpassoff', '$assertpasson', '$assertvacuousoff',
|
||
|
|
# Sampled value system functions (20.13)
|
||
|
|
'$changed', '$changed_gclk', '$changing_gclk', '$falling_gclk',
|
||
|
|
'$fell', '$fell_gclk', '$future_gclk', '$past', '$past_gclk',
|
||
|
|
'$rising_gclk', '$rose', '$rose_gclk', '$sampled', '$stable',
|
||
|
|
'$stable_gclk', '$steady_gclk',
|
||
|
|
# Coverage control functions (20.14)
|
||
|
|
'$coverage_control', '$coverage_get', '$coverage_get_max',
|
||
|
|
'$coverage_merge', '$coverage_save', '$get_coverage',
|
||
|
|
'$load_coverage_db', '$set_coverage_db_name',
|
||
|
|
# Probabilistic distribution functions (20.15)
|
||
|
|
'$dist_chi_square', '$dist_erlang', '$dist_exponential',
|
||
|
|
'$dist_normal', '$dist_poisson', '$dist_t', '$dist_uniform',
|
||
|
|
'$random',
|
||
|
|
# Stochastic analysis tasks and functions (20.16)
|
||
|
|
'$q_add', '$q_exam', '$q_full', '$q_initialize', '$q_remove',
|
||
|
|
# PLA modeling tasks (20.17)
|
||
|
|
'$async$and$array', '$async$and$plane', '$async$nand$array',
|
||
|
|
'$async$nand$plane', '$async$nor$array', '$async$nor$plane',
|
||
|
|
'$async$or$array', '$async$or$plane', '$sync$and$array',
|
||
|
|
'$sync$and$plane', '$sync$nand$array', '$sync$nand$plane',
|
||
|
|
'$sync$nor$array', '$sync$nor$plane', '$sync$or$array',
|
||
|
|
'$sync$or$plane',
|
||
|
|
# Miscellaneous tasks and functions (20.18)
|
||
|
|
'$system',
|
||
|
|
# Display tasks (21.2)
|
||
|
|
'$display', '$displayb', '$displayh', '$displayo', '$monitor',
|
||
|
|
'$monitorb', '$monitorh', '$monitoro', '$monitoroff',
|
||
|
|
'$monitoron', '$strobe', '$strobeb', '$strobeh', '$strobeo',
|
||
|
|
'$write', '$writeb', '$writeh', '$writeo',
|
||
|
|
# File I/O tasks and functions (21.3)
|
||
|
|
'$fclose', '$fdisplay', '$fdisplayb', '$fdisplayh',
|
||
|
|
'$fdisplayo', '$feof', '$ferror', '$fflush', '$fgetc', '$fgets',
|
||
|
|
'$fmonitor', '$fmonitorb', '$fmonitorh', '$fmonitoro', '$fopen',
|
||
|
|
'$fread', '$fscanf', '$fseek', '$fstrobe', '$fstrobeb',
|
||
|
|
'$fstrobeh', '$fstrobeo', '$ftell', '$fwrite', '$fwriteb',
|
||
|
|
'$fwriteh', '$fwriteo', '$rewind', '$sformat', '$sformatf',
|
||
|
|
'$sscanf', '$swrite', '$swriteb', '$swriteh', '$swriteo',
|
||
|
|
'$ungetc',
|
||
|
|
# Memory load tasks (21.4)
|
||
|
|
'$readmemb', '$readmemh',
|
||
|
|
# Memory dump tasks (21.5)
|
||
|
|
'$writememb', '$writememh',
|
||
|
|
# Command line input (21.6)
|
||
|
|
'$test$plusargs', '$value$plusargs',
|
||
|
|
# VCD tasks (21.7)
|
||
|
|
'$dumpall', '$dumpfile', '$dumpflush', '$dumplimit', '$dumpoff',
|
||
|
|
'$dumpon', '$dumpports', '$dumpportsall', '$dumpportsflush',
|
||
|
|
'$dumpportslimit', '$dumpportsoff', '$dumpportson', '$dumpvars',
|
||
|
|
), suffix=r'\b'),
|
||
|
|
Name.Builtin),
|
||
|
|
|
||
|
|
(r'[a-zA-Z_]\w*:(?!:)', Name.Label),
|
||
|
|
(r'\$?[a-zA-Z_]\w*', Name),
|
||
|
|
(r'\\(\S+)', Name),
|
||
|
|
],
|
||
|
|
'string': [
|
||
|
|
(r'"', String, '#pop'),
|
||
|
|
(r'\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})', String.Escape),
|
||
|
|
(r'[^\\"\n]+', String), # all other characters
|
||
|
|
(r'(\\)(\n)', bygroups(String.Escape, Whitespace)), # line continuation
|
||
|
|
(r'\\', String), # stray backslash
|
||
|
|
],
|
||
|
|
'macro': [
|
||
|
|
(r'[^/\n]+', Comment.Preproc),
|
||
|
|
(r'/[*](.|\n)*?[*]/', Comment.Multiline),
|
||
|
|
(r'//.*?$', Comment.Single, '#pop'),
|
||
|
|
(r'/', Comment.Preproc),
|
||
|
|
(r'(?<=\\)\n', Comment.Preproc),
|
||
|
|
(r'\n', Whitespace, '#pop'),
|
||
|
|
],
|
||
|
|
'import': [
|
||
|
|
(r'[\w:]+\*?', Name.Namespace, '#pop')
|
||
|
|
]
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
class VhdlLexer(RegexLexer):
|
||
|
|
"""
|
||
|
|
For VHDL source code.
|
||
|
|
"""
|
||
|
|
name = 'vhdl'
|
||
|
|
aliases = ['vhdl']
|
||
|
|
filenames = ['*.vhdl', '*.vhd']
|
||
|
|
mimetypes = ['text/x-vhdl']
|
||
|
|
url = 'https://en.wikipedia.org/wiki/VHDL'
|
||
|
|
version_added = '1.5'
|
||
|
|
flags = re.MULTILINE | re.IGNORECASE
|
||
|
|
|
||
|
|
tokens = {
|
||
|
|
'root': [
|
||
|
|
(r'\s+', Whitespace),
|
||
|
|
(r'(\\)(\n)', bygroups(String.Escape, Whitespace)), # line continuation
|
||
|
|
(r'--.*?$', Comment.Single),
|
||
|
|
(r'/(\\\n)?[*](.|\n)*?[*](\\\n)?/', Comment.Multiline),
|
||
|
|
(r"'(U|X|0|1|Z|W|L|H|-)'", String.Char),
|
||
|
|
(r'[~!%^&*+=|?:<>/-]', Operator),
|
||
|
|
(r"'[a-z_]\w*", Name.Attribute),
|
||
|
|
(r'[()\[\],.;\']', Punctuation),
|
||
|
|
(r'"[^\n\\"]*"', String),
|
||
|
|
|
||
|
|
(r'(library)(\s+)([a-z_]\w*)',
|
||
|
|
bygroups(Keyword, Whitespace, Name.Namespace)),
|
||
|
|
(r'(use)(\s+)(entity)', bygroups(Keyword, Whitespace, Keyword)),
|
||
|
|
(r'(use)(\s+)([a-z_][\w.]*\.)(all)',
|
||
|
|
bygroups(Keyword, Whitespace, Name.Namespace, Keyword)),
|
||
|
|
(r'(use)(\s+)([a-z_][\w.]*)',
|
||
|
|
bygroups(Keyword, Whitespace, Name.Namespace)),
|
||
|
|
(r'(std|ieee)(\.[a-z_]\w*)',
|
||
|
|
bygroups(Name.Namespace, Name.Namespace)),
|
||
|
|
(words(('std', 'ieee', 'work'), suffix=r'\b'),
|
||
|
|
Name.Namespace),
|
||
|
|
(r'(entity|component)(\s+)([a-z_]\w*)',
|
||
|
|
bygroups(Keyword, Whitespace, Name.Class)),
|
||
|
|
(r'(architecture|configuration)(\s+)([a-z_]\w*)(\s+)'
|
||
|
|
r'(of)(\s+)([a-z_]\w*)(\s+)(is)',
|
||
|
|
bygroups(Keyword, Whitespace, Name.Class, Whitespace, Keyword, Whitespace,
|
||
|
|
Name.Class, Whitespace, Keyword)),
|
||
|
|
(r'([a-z_]\w*)(:)(\s+)(process|for)',
|
||
|
|
bygroups(Name.Class, Operator, Whitespace, Keyword)),
|
||
|
|
(r'(end)(\s+)', bygroups(using(this), Whitespace), 'endblock'),
|
||
|
|
|
||
|
|
include('types'),
|
||
|
|
include('keywords'),
|
||
|
|
include('numbers'),
|
||
|
|
|
||
|
|
(r'[a-z_]\w*', Name),
|
||
|
|
],
|
||
|
|
'endblock': [
|
||
|
|
include('keywords'),
|
||
|
|
(r'[a-z_]\w*', Name.Class),
|
||
|
|
(r'\s+', Whitespace),
|
||
|
|
(r';', Punctuation, '#pop'),
|
||
|
|
],
|
||
|
|
'types': [
|
||
|
|
(words((
|
||
|
|
'boolean', 'bit', 'character', 'severity_level', 'integer', 'time',
|
||
|
|
'delay_length', 'natural', 'positive', 'string', 'bit_vector',
|
||
|
|
'file_open_kind', 'file_open_status', 'std_ulogic', 'std_ulogic_vector',
|
||
|
|
'std_logic', 'std_logic_vector', 'signed', 'unsigned'), suffix=r'\b'),
|
||
|
|
Keyword.Type),
|
||
|
|
],
|
||
|
|
'keywords': [
|
||
|
|
(words((
|
||
|
|
'abs', 'access', 'after', 'alias', 'all', 'and',
|
||
|
|
'architecture', 'array', 'assert', 'attribute', 'begin', 'block',
|
||
|
|
'body', 'buffer', 'bus', 'case', 'component', 'configuration',
|
||
|
|
'constant', 'disconnect', 'downto', 'else', 'elsif', 'end',
|
||
|
|
'entity', 'exit', 'file', 'for', 'function', 'generate',
|
||
|
|
'generic', 'group', 'guarded', 'if', 'impure', 'in',
|
||
|
|
'inertial', 'inout', 'is', 'label', 'library', 'linkage',
|
||
|
|
'literal', 'loop', 'map', 'mod', 'nand', 'new',
|
||
|
|
'next', 'nor', 'not', 'null', 'of', 'on',
|
||
|
|
'open', 'or', 'others', 'out', 'package', 'port',
|
||
|
|
'postponed', 'procedure', 'process', 'pure', 'range', 'record',
|
||
|
|
'register', 'reject', 'rem', 'return', 'rol', 'ror', 'select',
|
||
|
|
'severity', 'signal', 'shared', 'sla', 'sll', 'sra',
|
||
|
|
'srl', 'subtype', 'then', 'to', 'transport', 'type',
|
||
|
|
'units', 'until', 'use', 'variable', 'wait', 'when',
|
||
|
|
'while', 'with', 'xnor', 'xor'), suffix=r'\b'),
|
||
|
|
Keyword),
|
||
|
|
],
|
||
|
|
'numbers': [
|
||
|
|
(r'\d{1,2}#[0-9a-f_]+#?', Number.Integer),
|
||
|
|
(r'\d+', Number.Integer),
|
||
|
|
(r'(\d+\.\d*|\.\d+|\d+)E[+-]?\d+', Number.Float),
|
||
|
|
(r'X"[0-9a-f_]+"', Number.Hex),
|
||
|
|
(r'O"[0-7_]+"', Number.Oct),
|
||
|
|
(r'B"[01_]+"', Number.Bin),
|
||
|
|
],
|
||
|
|
}
|